Friday, 9 August 2013

Over Voltage Protection circuit. Schematic + Proteus Simulation.

This post is all about how to protect your circuit from over voltage or a surge in DC voltage. This is analog circuit based on some basic components. You may download Schematic and Proteus simulation from the download section given at the bottom of this page. There are two basic methods to cut the supply to your circuit when an over voltage is detected.

1)      Cut down the Positive terminal.
2)      Cut down the GND terminal.

Cutting down the GND terminal is not a good design habit when you have multiple source of power although it is easy. So it’s better to have a positive terminal disconnecting circuit in case of overvoltage detection.

Proteus Simulation:

In the following figure 1. We have some basic circuit for over voltage protection. This circuit is designed to cut the circuit if the input voltage is greater than 27V. So for simulating this we have two batteries one is 24VDC and other one is 30VDC. Which is connected with a switch. Now by the help of this switch we will trigger the overvoltage cutoff circuit. As we have to cut positive terminal so I am using P-MOSFET Q1. As SCR has a drop of 0.3V-0.7V so we may not use this directly to the base of transistor connected to gate of P-MOS. Therefore I used an additional N-MOS for proper shutdown of circuit. One Zener Diode is also used named D1 of voltage 27V. You may change this diode according to you design requirement eg. For 14VDC overvoltage circuit you may use zener of 14VDC. A dummy load is attached and a voltmeter is used to verify the simulation results easily.

Figure 1. Schematic.

Now in the following figure 2. Red track shows the high terminals and green tracks shows the ground terminals whereas arrows shows the direction of flow of current. You may have notice that when input voltage is 24VDC (less than threshold voltage 27VDC) we have 24VDC at the terminals of dummy load. In this state the Q1 MOSFET is ON, which has a condition of VGS < 0 volts. On the other hand the N-Mos is also Conducting, which has a condition of VGS > 0. You may also noticed that SCR and zener are not conducting hence the circuit is working under normal input voltage.

Figure 2. Proteus Simulation under normal input voltage.
In the following figure 3. When I switched the input supply to the 30VDC source this causes the over voltage circuit to trigger and hence zener diode passes the current and SCR is triggered which ultimately cut down the N-MOS and transistor Q2 has zero voltage at its base. Now the P-MOS has off Condition VGS = 0. The voltmeter is showing there is no voltage at dummy load.
Figure 3. Proteus Simulation over voltage circuit triggered.


You can download Schematic and Proteus (v8) Simulation. Clickhere

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